The present invention relates to a voltage controlled oscillator (VCO) and, in particular, it relates to a voltage controlled oscillator that may be used for a phase-locked loop (PLL).
Voltage controlled oscillators that are formed by connecting in series an odd number of complementary type MOS inverters in a ring, are disclosed in Japanese Unexamined Patent Publication No 268002/1993 and the like The voltage controlled oscillator (hereafter referred to as "VCO") 101 disclosed in the publication above is explained in reference to FIGS. 9 and 10.
This VCO 101 is constituted of inverter circuits 111, 112 and 113 which are connected in series in a ring forming a loop. It is to be noted that the inverter circuits 111, 112 and 113 are structured almost identically to one another and, therefore, only the structure of the inverter circuit 111 will be explained here as a representative example.
The inverter circuit 111 is provided with a PMOS transistor P1, an NMOS transistor N1 and an NMOS transistor N10.
The gates of the PMOS transistor P1 and the NMOS transistor N1 are commonly connected to an input IN 111 of the inverter circuit 111, whereas the drains of the PMOS transistor P1 and the NMOS transistor N1 are commonly connected to an output OUT 111 of the inverter circuit 111. The source of the PMOS transistor P1 is connected to a source voltage level VD and the source of the NMOS transistor N1 is connected to the drain of the NMOS transistor N10.
In addition, the source of the NMOS transistor N10 is connected to a ground level, and a control signal VCN is input to its gate. It is to be noted that this control signal VCN is also input to the inverter circuits 112 and 113, being connected to the gates of their NMOS transistors (not shown) which have functions and structural features identical to those of the NMOS transistor N10 in the inverter circuit 111.
The output OUT 111 of the inverter circuit 111 which is structured as described above, is connected to an input IN 112 of the inverter circuit 112, the output OUT 112 of the inverter circuit 112 is connected to an input IN 113 of the inverter circuit 113 and an output OUT 113 of the inverter circuit 113 is connected to the input IN 111 of the inverter circuit 111. In other words, the VCO 101 is constituted as a ring oscillator in which the inverter circuits 111, 112 and 113 are connected in a ring.
Now, the oscillating frequency (f) of the VCO 101 is expressed as 1/(td* n), with (td) representing the transmission delay time corresponding to one stage of the inverter circuit and (n) representing the number of stages of the inverter circuit. In addition, the transmission delay time (td) of the inverter circuits 111, 112 and 113 is dependent upon the voltage level of the control signal VCN.
For instance, when the voltage level (Vc) of the control signal VCN is reduced, the on resistance of the NMOS transistor N10 increases, thereby lengthening the fall time of the voltage levels of the individual output signals at the outputs OUT 111, 112 and 113 of the inverter circuits 111, 112 and 113 respectively. This increases the transmission delay time (td) and, as a result, the oscillating frequency (f) of the VCO 101 is reduced. If, on the other hand, the voltage level of the control signal VCN is increased, the on resistance of the NMOS transistor N10 becomes lower, thereby shortening the fall time of the voltage levels at the outputs OUT 111, 112 and 113 of the inverter circuits 111, 112 and 113 respectively. Thus, the transmission delay time (td) is reduced and, as a result, the oscillating frequency (f) of the VCO 101 becomes higher.
Since different clock frequencies are normally required for individual systems in which the VCO 101 is employed, it is necessary to broaden the band of the oscillating frequency (f) in order to achieve a versatile VCO 101 which can be adopted in a number of different systems. For instance, in order to support two systems, i.e., one with a clock frequency of 100 MHz and the other with a clock frequency of 300 MHz, the oscillating frequency (f) must change within the range of, at least, 100 MHz-300 MHz relative to the voltage level variable width of the control signal VCN, e.g., 0-3.3 V, as shown in FIG. 10.
However, when such a wide oscillating frequency (f) band is to be covered, the amount of change in the oscillating frequency (f) relative to the voltage level (Vc) of the control signal VCN (hereafter referred to as the "VCO gain": VCO gain=f/Vc) increases, the oscillating frequency (f) is caused to fluctuate greatly by a minute fluctuation in the voltage level (Vc) of the control signal VCN. Such a fluctuation of the oscillating frequency (f) may cause jitter, which may, in turn, detract from the stability of the system.
In addition, if the band of the oscillating frequency (f) is reduced in order to eliminate the problem discussed above, the versatility of the VCO will be sacrificed, which may present difficulty in obtaining a desired oscillating frequency. Thus, since it is necessary to optimize the oscillating frequency of the VCO to support the frequency required by the system in which the VCO is to be incorporated, a new VCO must be designed for every case.